A limiting factor in the useful life and long term reliability of integrated circuit structures is the migration of materials in the vicinity of metal to silicon contacts caused by the transport characteristics of electrons. This "electromigration" is characterized by physical movement of constituent metal and silicon molecules from different layers through the IC structure. Joule heating from high currents may also cause thermal diffusion or "thermomigration" of the metal and silicon molecules.
Aluminum and aluminum alloys are typically used for the metal layer contacts and have a tendency to "alloy" with silicon. Aluminum may migrate through the metal-semiconductor interface into the underlying silicon, alloying with the silicon. The metal to silicon ohmic contact typically incorporates a step configuration perimeter where the metal layer is applied through an opening in an insulating oxide layer to an underlying active silicon region. Deterioration of the metal layer causes increased resistance of the metal contact particularly at the step locus. The step locus is a site vulnerable to deterioration because current density there may be twice that of other locations aggravating the electromigration of aluminum. This deterioration in the surface metal contact and step coverage and increase in contact resistance leads gradually to a first type of failure or first failure mode by increase in contact resistance beyond the permitted specification for a particular wafer fabrication process.
A second failure mode is caused by migration of the silicon into the metal layer and vice-versa causing voids in the epitaxial layer or substrate and at underlying or adjacent PN junctions. Such voids at a PN junction are referred to as junction "spiking" or "poisoning" and can lead to catastrophic failure with dramatic rise in current across the pN junction.
Steps which have been taken to retard this deterioration and to increase useful life of integrated circuit structures include the use of a titanium-tungsten (Ti--W) layer and other barrier layers between the aluminum and silicon as diffusion/migration barriers. Aluminum alloys such as copper aluminum alloys and silicon aluminum alloys are also used for the metal layers to prevent further alloying of the metal with active area silicon. These expedients only slow the process however, and assessment of the reliability of the integrated circuit metal to silicon contacts at the wafer level is still essential. Process variation in CMOS or BICMOS wafer fabrication processes may result in poor contact step coverage or other detrimental effects. It is therefore desirable to provide testing of the reliability of metal to silicon contacts of dies on wafers at the wafer level for assessment of the particular process quality.
A typical CMOS wafer fabrication process generally follows the following mask sequence and associated mask steps set forth in TABLE I. A further description is found in the Jeffrey B. Davis and Stephen C. Park U.S. patent application Ser. No. 713,027, filed Jun. 7, 1991, a division of U.S. patent application Ser. No. 510,227,filed Apr. 17, 1990 for ELECTROSTATIC DISCHARGE PROTECTION TRANSISTOR ELEMENT AND FABRICATION PROCESS, and in the Murray J. Robinson and Christopher C. Joyce U.S. patent application Ser. No. 802,878 filed Dec. 6, 1991 for HIGH DEFINITION HIGH RESISTANCE RESISTOR STRUCTURE AND FABRICATION PROCESS.
TABLE I ______________________________________ CMOS WAFER FABRICATION MASK SEQUENCES Mask No. Mask Function/Name ______________________________________ 0 PWELL Definition Mask 1.0 Active Area Definition Mask 2.0 PWELL Field Implant Mask 3.0 Poly Definition Mask (Gate Definition Mask For CMOS Transistors) 4.0 N.sup.+ S/D Source/Drain Implant Mask (Self-Aligned NMOS Transistor Mask) 4.1 P.sup.+ S/D Source/Drain Implant Mask (Self-Aligned PMOS Transistor Mask) 5.0 Contact Definition Mask 6.0 Metal 1 (M1) Definition Mask 7.0 VIA Mask (Second Contact Definition Mask) 8.0 Metal 2 (M2) Definition Mask 9.0 Passivation Definition ______________________________________
The CMOS wafer fabrication process typically begins with a substrate of N type silicon semiconductor material prepared with an N- silicon epitaxial layer and thin protective layers of thermally grown silicon dioxide SiO.sub.2 and silicon nitride Si.sub.3 N.sup.4. A photoresist layer is "spun on" and patterned to provide the 0 Mask or PWELL Definition Mask defining the P- type wells or PWELLS for NMOS transistor elements. The nitride layer is stripped in a dry etch over the PWELL area and PWELLS are established by a P- boron ion implant. As used herein the plus and minus signs indicate the relative concentration of N type or P type dopant material in the respective silicon semiconductive region and the relative conductivity of the silicon regions. In subsequent steps an N- implant of N type dopant material ions such as phosphorus ions establishes the N- type wells or NWELLS for PMOS transistor elements outside the PWELL areas.
In due course a new nitride layer is deposited and the nitride layer is patterned and etched using the photoresist 1.0 Active Area Definition Mask. The Active Area Definition Mask and etch step leaves islands of silicon nitride over the PWELLS AND NWELLS coinciding with the active areas for NMOS and PMOS transistor elements respectively. The 1.0 Mask and resulting nitride islands define the channel width of the respective NMOS & PMOS transistor elements.
The photoresist 2.0 PWELL Field Implant Mask is next formed covering the NWELLS followed by the P+ field implant. The 2.0 PWELL Field Implant Mask, also referred to as the N Channel Field Implant Mask, is similar to the 0 Mask or PWELL Definition Mask but leaves openings slightly larger for example 2u beyond the original PWELL areas. The P+ field implant establishes P+ channel stop regions to increase the threshold voltage or turn on voltage V.sub.TON of parasitic transistor structures that arise between active areas across the field oxide. Following the P+ field implant and stripping of the 2.0 Mask the field oxide regions are grown between the nitride islands. The field oxide or FOX surrounds the nitride islands for isolating the active areas. The nitride islands prevent growth of FOX in the active areas of the NMOS and PMOS transistor elements. The nitride islands are then stripped from the chip and other steps follow.
A poly layer is patterned using the 3.0 Poly Definition Mask, and the poly definition mask and etch steps leave gates of polysilicon over the active areas. The poly gates are smaller than the active areas of the respective transistor elements and define the channel length of the respective transistor elements. The photoresist 3.0 Poly Definition Mask thus also functions as the gate definition mask for CMOS transistor elements.
The poly gates for the NMOS transistor elements over the PWELLS in combination with the photoresist 4.0 N+S/D Source/Drain Implant Mask provide a self-aligned transistor mask for the NMOS transistor elements. An N+implant follows establishing the N+drain and source regions for the NMOS transistor elements.
The photoresist 4.1 P+S/D Source/Drain Implant Mask is similar to the 4.0 Mask but covers the PWELLS and active areas for the NMOS transistor elements. In effect the 4.1 Mask and associated 4.1 Mask steps are the inverse of the 4.0 Mask and associated 4.0 Mask steps.
Upon completion of implant of the source and drain regions, the photoresist 4.0 and 4.1 Masks are stripped and a blanket passivating layer of for example, low temperature semiconductor material oxide (LTO) is deposited. The LTO or other passivating material may be deposited by chemical vapor deposition. The blanket passivating layer is patterned and etched using the photoresist 5.0. Contact Definition Mask for defining and establishing the openings in the LTO or other passivating material layer for metal contacts from the Metal 1 or M1 layer.
For the CMOS transistor elements, the LTO layer provides an insulating passivating layer over the poly gate and between the poly gate and M1 layer. The 5.0 Contact Definition Mask defines the metal conductor contacts to the source and drain regions. The first metal layer is deposited over the patterned passivating layer and the Metal 1 or M1 layer is masked and etched using the 6.0 M1 Definition Mask leaving the source and drain metal contacts and conductors which may be formed in the step configuration.
A second LTO layer or other interlayer dielectric (ILD) material layer is deposited, masked and etched using the 7.0 VIA Mask which defines openings for contacts between a second metal layer or M2 layer and the M1 layer including the openings for bond pads. The 7.0 VIA Mask is a second contact definition mask for the second LTO or ILD layer. The second metal layer is deposited, masked and etched using the photoresist 8.0 M2 Definition Mask. The second metal layer M2 in parallel with the first metal layer M1 reduces current density etc. The final steps include depositing a passivating nitride layer over the entire chip followed by the photoresist 9.0 Passivation Definition Mask and etch steps for opening the bond pads.
A BICMOS IC fabrication process for fabricating both bipolar and CMOS transistor structures currently in use at National Semiconductor Corporation, South Portland, Me. 04106 is summarized in TABLE II showing the overall BICMOS mask sequence and associated mask steps. Further description of the BICMOS process mask sequences is found in the Murray J. Robinson, Christopher C. Joyce, and Tim Wah Luk U.S. patent application Ser. No. 655,676 filed Feb. 14, 1991 for BIPOLAR TRANSISTOR STRUCTURE AND BICMOS IC FABRICATION PROCESS, and the Robinson, Joyce, and Luk U.S. patent application Ser. No. 803,214 filed Dec. 6, 1991 for SCHOTTKY DIODE STRUCTURE AND FABRICATION PROCESS.
TABLE II ______________________________________ BICMOS WAFER FABRICATION MASK SEQUENCES Mask No. Mask Function ______________________________________ 1.0 Buried Collector Layer (BCL) Mask 2.0 Retro NWELL Mask and Retro SEC Mask 3.0 Retro PWELL/Channel Stop (CHST) Mask 4.0 Isolation Oxide (ISOX) Mask 5.0 Sink Implant & ISOX Gettering Mask 6.0 CMOS Active Area Definition Mask (Field Oxide Mask) & Collector Base Surface Spacer (CBSS) Definition Mask 7.0 Active Strip Mask 8.0 Poly Gate Definition Mask 9.0 Base Definition Mask 10.0 Nitride Etch Mask or Collector Base & Emitter Contact Definition Mask 11.0 Emitter & Collector Sink Implant Mask (Self-Aligned Transistor Mask) 12.0 N+S/D Source/Drain Mask (NMOS) 13.0 P+S/D Source/Drain Mask (PMOS) 14.0 CMOS Contact Definition Mask 15.0 METAL 1 (M1) Deposition Mask 16.0 VIA Mask (Inter Layer Dielectric Mask) 17.0 METAL 2 (M2) Deposition Mask 18.0 Passivation Mask ______________________________________
A buried collector layer BCL for bipolar transistors is formed typically in P type substrate using the 1.0 BCL mask etch and implant sequence at the beginning of the BICMOS wafer fabrication process. Relatively slow diffusing N type antimony atoms are implanted in the P type substrate to an N+ concentration through an initial oxide layer. A new photoresist layer is then deposited to form the 2.0 mask. The 2.0 NWELL mask sequence provides not only the retro NWELL definition and implant mask with an NWELL opening for the CMOS transistor structure, but also a subemitter collector (SEC) region definition and implant mask with an SEC opening for the bipolar transistor structure. By way of example the SEC opening in the 2.0 mask is formed with a horizontal area of approximately 10% and preferably in the range of 10% to 20% of the horizontal cross section area of the BCL. Relatively fast diffusing phosphorous atoms are implanted to an N+ concentration level through the 2.0 mask. Phosphorous atoms are used for the N+ concentration implant of the SEC and NWELL regions for faster up diffusion during subsequent annealing steps as hereafter described to provide retrograde concentrations extending into the subsequently deposited epitaxial EPI.
The 3.0 mask, etch and implant sequence or 3.0 PWELL mask sequence is used for defining and implanting the retro PWELL region of the CMOS transistor structure and the channel stop regions CHST adjacent to the bipolar transistor structure. Boron atoms are implanted to a P+ concentration level in the PWELL and CHST regions. A single crystal epitaxial layer of N- silicon is then deposited uniformly over the BICMOS IC structure in a blanket epitaxial deposition without a mask.
Isolation oxide regions are established around the bipolar transistor structures using the 4.0 isolation oxide mask, etch and oxidation sequence. The collector sink region CS is implanted with an N+ concentration of phosphorous atoms using the 5.0 sink mask, etch and implant sequence The 5.0 mask is also formed for implanting the isolation oxide regions ISOX with the phosphorous atoms as a gettering agent. A uniform nitride layer is deposited in a blanket chemical vapor deposition across the BICMOS structure.
The 6.0 Active Area Definition Mask or Active Mask is formed for etching the nitride layer and defining the active regions of the CMOS transistor structure. The openings in the 6.0 active mask define the framing field oxide regions FOX for framing the CMOS transistor structures during the subsequent oxidation step.
At the same time the 6.0 active mask also functions as the collector base surface spacer region CBSS definition mask for the bipolar transistor structure. In the subsequent field oxidation step, the collector base surface spacer region CBSS is formed from the field oxide rather than isolation oxide.
In the 7.0 active strip mask steps the nitride layer is stripped except over the bipolar transistor structure and the active areas of the CMOS transistor structure are opened to expose the epitaxial silicon. The gate oxide layer GOX is grown and polysilicon (POLY) is deposited in one or two layers with doping to adjust the threshold voltage for the CMOS transistor structure. The 8.0 poly gate definition mask steps define the gates for CMOS transistors using a photoresist layer and photolithographic stepper followed by etching the poly layer and leaving behind the poly gates over the gate oxide layer. A thin oxide layer referred to as a sealing oxide or spacer oxide is grown over the poly gates.
The 9.0 base mask, etch and implant sequence is used for defining and implanting the base of the bipolar transistor structure with P type boron atoms. The 10.0 nitride etch mask provides a collector, base and emitter contact definition mask which is a self-aligned transistor (SAT) nitride mask over the bipolar transistor structure. The epitaxial oxide layer EPIOX remains over the bipolar transistor structure with the nitride mask defining the collector, base and emitter contacts.
The 11.0 emitter and collector sink implant mask is modified to utilize the underlying nitride SAT mask over the bipolar transistor structure. The emitter and collector sink regions are implanted to an N+ concentration level with N type arsenic atoms. While previous annealing steps have begun development of the retrograde concentration upward from the PWELL, NWELL, and the SEC region, the subsequent annealing step following implant of the emitter and collector sink regions fully develops most of the retrograde concentration profile of dopant atoms.
A blanket N- arsenic implant precedes the 12.0 N+S/D source/drain mask, etch and implant sequence for the NMOS transistor elements. The N+S/D source/drain implant is a phosphorous implant over the arsenic. The combination of the N- arsenic implant and N+ phosphorous implant develops a profiled lightly doped drain for the NMOS transistor element of the CMOS transistor pair. The 13.0 P+S/D source/drain mask, etch and implant sequence is used for implanting the source and drain regions of the PMOS transistor structure.
Following the source/drain mask, etch and implant sequences for the NMOS and PMOS transistor elements of the CMOS transistor structure, a blanket low temperature oxide layer LTO is deposited over the BICMOS structure. The 14.0 CMOS contact definition mask and etch sequence removes the LTO over the CMOS metal contact areas and over the bipolar transistor structure. The SAT nitride mask remains permanently on the bipolar transistor structure for defining the bipolar transistor metal contact areas. In subsequent mask steps the first metal layer is deposited using the Metal 1 or M1 mask and deposition sequence followed by blanket deposition of an interlayer dielectric (ILD). The ILD is masked and etched using the 16.0 VIA mask followed by deposition of the second metal layer using the 17.0 Metal 2 or M2 mask and deposition sequence. The final 18.0 passivation etch and mask sequence cuts holes in the nitride layer for bond pads.